View CY62256LL-70SNXCT_8152371.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

256k (32k x 8) static ram cy62256 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 ? 408-943-2600 document #: 38-05248 rev. *e revised july 14, 2005 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? high speed: 55 ns and 70 ns ? voltage range: 4.5v?5.5v operation ? low active power (70 ns, ll version, com?l and ind?l) ? 275 mw (max.) ? low standby power (70 ns, ll version, com?l and ind?l) ? 28 w (max.) ? easy memory expansion with ce and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected ? cmos for optimum speed/power ? package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow soic, 28-lead tsop-1, 28-lead reverse tsop-1, and 600-mil 28-lead pdip packages ? also available in lead-free packages functional description [1] the cy62256 is a high-performance cmos static ram organized as 32k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and three-state drivers. this device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins are present on th e eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 512 x 512 arra y i/o 7 i/o 6 i/o 5 i/o 4 a 10 a 13 a 11 a 12 a a 14 a 1 0 logic block diagram
cy62256 document #: 38-05248 rev. *e page 2 of 13 pin configurations product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) min. typ. [2] max. typ. [2] max. typ. [2] max. cy62256 commercial 4.5 5.0 5.5 70 28 55 1 5 cy62256l com?l / ind?l 55/70 25 50 2 50 cy62256ll commercial 70 25 50 0.1 5 cy62256ll industrial 55/70 25 50 0.1 10 cy62256ll automotive 55 25 50 0.1 15 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view narrow soic 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 tsop i top view (not to scale) reverse pinout 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 tsop i top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view dip 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 pin definitions pin number type description 1?10, 21, 23?26 input a 0 ?a 14 . address inputs 11?13, 15?19, input/output i/o 0 ?/o 7 . data lines. used as input or ou tput lines depending on operation 27 input/control we . when selected low, a write is cond ucted. when selected high, a read is conducted 20 input/control ce . when low, selects the chip. when high, deselects the chip 22 input/control oe . output enable. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins 14 ground gnd . ground for the device 28 power supply v cc . power supply for the device note: 2. typical specifications are the mean values measured over a larg e sample size across normal production process variations and are taken at nominal conditions (t a = 25 c, v cc ). parameters are guaranteed by design and characterization, and not 100% tested.
cy62256 document #: 38-05248 rev. *e page 3 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied..............................................-55 c to +125 c supply voltage to ground potential (pin 28 to pin 14) ........................................... ?0.5v to +7.0v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] .................................?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature (t a ) [4] v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c 5v 10% automotive ?40 c to +125 c 5v 10% electrical characteristics over the operating range parameter description test conditions cy62256 ? 55 cy62256 ? 70 unit min. typ. [2] max. min. typ. [2] max. v oh output high voltage v cc = min., i oh = ? 1.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 2.1 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.5v 2.2 v cc +0.5v v v il input low voltage ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?0.5 +0.5 ?0.5 +0.5 a i oz output leakage current gnd < v o < v cc , output disabled ?0.5 +0.5 ?0.5 +0.5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 28 55 28 55 ma l25502550ma ll 25 50 25 50 ma i sb1 automatic ce power-down current? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 0.5 2 0.5 2 ma l0.40.60.40.6ma ll 0.3 0.5 0.3 0.5 ma i sb2 automatic ce power-down current? cmos inputs max. v cc , ce > v cc ? 0.3v v in > v cc ? 0.3v, or v in < 0.3v, f = 0 15 15ma l250250 a ll 0.1 5 0.1 5 a ll - ind?l 0.1 10 0.1 10 a ll - auto 0.1 15 a capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 6pf c out output capacitance 8 pf thermal resistance parameter description test conditions dip soic tsop rtsop unit ja thermal resistance (junction to ambient) [5] still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board 75.61 76.56 93.89 93.89 c/w jc thermal resistance (junction to case) [5] 43.12 36.07 24.64 24.64 c/w notes: 3. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 4. t a is the ?instant-on? case temperature. 5. tested initially and after any design or process changes that may affect these parameters.
cy62256 document #: 38-05248 rev. *e page 4 of 13 ac test loads and waveforms data retention characteristics parameter description conditions [6] min. typ. [2] max. unit v dr v cc for data retention 2.0 v i ccdr data retention current l v cc = 3.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v 250 a ll 0.1 5 a ll - ind?l 0.1 10 a ll - auto 0.1 10 a t cdr [5] chip deselect to data retention time 0 ns t r [5] operation recovery time t rc ns 3.0v 5v output r1 1800 ? r2 990 ? 100 pf including jig and scope gnd 90% 10% 90% 10% <5ns <5 ns 5v output r1 1800 ? r2 990 ? 5pf including jig and scope (a) (b) output 1.77v equivalent to: th venin equivalent all input pulses 639 ? data retention waveform note: 6. no input may exceed v cc + 0.5v. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc
cy62256 document #: 38-05248 rev. *e page 5 of 13 switching characteristics over the operating range [7] parameter description cy62256 ? 55 cy62256 ? 70 unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low-z [8] 55ns t hzoe oe high to high-z [8, 9] 20 25 ns t lzce ce low to low-z [8] 55ns t hzce ce high to high-z [8, 9] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns write cycle [10, 11] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 50 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [8, 9] 20 25 ns t lzwe we high to low-z [8] 55ns switching waveforms read cycle no. 1 [12, 13] notes: 7. test conditions assume signal transition ti me of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 100-pf load capacitance. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 10. the internal write time of the me mory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 11. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha
cy62256 document #: 38-05248 rev. *e page 6 of 13 read cycle no. 2 [13, 14] write cycle no. 1 (we controlled) [10, 15, 16] write cycle no. 2 (ce controlled) [10, 15, 16] notes: 14. address valid prior to or coincident with ce transition low. 15. data i/o is high impedance if oe = v ih . 16. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 17. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance icc isb t hzoe t hzce t pd oe ce high v cc supply current t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 17 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid
cy62256 document #: 38-05248 rev. *e page 7 of 13 write cycle no. 3 (we controlled, oe low) [11, 16] switching waveforms (continued) data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 17
cy62256 document #: 38-05248 rev. *e page 8 of 13 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 ? 55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature ambient temperature ( c) output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i cc normalized i cc , i sb i cc i cc v cc = 5.0v v cc = 5.0v t a = 25 c v cc = 5.0v t a = 25 c i sb t a = 25 c 0.6 0.8 0 1.3 1.2 v in = 5.0v t a = 25 c 1.4 v cc = 5.0v v in = 5.0v ? 55 25 105 2.5 2.0 1.5 current vs. ambient temperature ambient temperature ( c) 1.0 0.5 0.0 ?0.5 i sb 3.0 standby v cc = 5.0v v in = 5.0v i sb2 a
cy62256 document #: 38-05248 rev. *e page 9 of 13 typical dc and ac characteristics (continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) 0.0 5.0 0.0 1000 0.50 v cc = 4.5v t a = 25 c v cc =5.0v t a = 2 5 c v in = 0.5v normalized i cc vs. cycle time truth table ce we oe inputs/outputs mode power h x x high-z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high-z output disabled active (i cc )
cy62256 document #: 38-05248 rev. *e page 10 of 13 \ ordering information speed (ns) ordering code package name package type operating range 55 cy62256ll ? 55sni sn28 28-lead (300-mil narrow body) narrow soic industrial cy62256ll ? 55snxi sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256ll ? 55zi z28 28-lead thin small outline package cy62256ll ? 55zxi z28 28-lead thin small outline package (pb-free) cy62256ll ? 55sne sn28 28-lead (300-mil narrow body) narrow soic automotive cy62256ll ? 55snxe sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256ll ? 55ze z28 28-lead thin small outline package cy62256ll ? 55zxe z28 28-lead thin small outline package (pb-free) cy62256ll ? 55zre zr28 28-lead reverse thin small outline package cy62256ll ? 55zrxe zr28 28-lead reverse thin small outline package (pb-free) 70 cy62256 ? 70snc sn28 28-lead (300-mil narrow body) narrow soic commercial cy62256l ? 70snc sn28 28-lead (300-mil narrow body) narrow soic cy62256l ? 70snxc sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256ll ? 70snc sn28 28-lead (300-mil narrow body) narrow soic cy62256ll ? 70snxc sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256l?70sni sn28 28-lead (300-mil narrow body) narrow soic industrial cy62256l?70snxi sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256ll ? 70sni sn28 28-lead (300-mil narrow body) narrow soic cy62256ll ? 70snxi sn28 28-lead (300-mil narrow body) narrow soic (pb-free) cy62256ll ? 70zc z28 28-lead thin small outline package commercial cy62256ll ? 70zxc z28 28-lead thin small outline package (pb-free) cy62256ll ? 70zi z28 28-lead thin small outline package industrial cy62256ll ? 70zxi z28 28-lead thin small outline package (pb-free) cy62256 ? 70pc p15 28-lead (600-mil) molded dip commercial cy62256l ? 70pc p15 28-lead (600-mil) molded dip cy62256l ? 70pxc p15 28-lead (600-mil) molded dip (pb-free) cy62256ll ? 70pc p15 28-lead (600-mil) molded dip cy62256ll ? 70pxc p15 28-lead (600-mil) molded dip (pb-free) cy62256ll ? 70zri zr28 28-lead reverse thin small outline package industrial cy62256ll ? 70zrxi zr28 28-lead reverse thin small outline package (pb-free)
cy62256 document #: 38-05248 rev. *e page 11 of 13 package diagrams 51-85017-*a 28-lead (600-mil) molded dip p15 51-85092-*b 28-lead (300-mil) s nc (narrow body) sn28
cy62256 document #: 38-05248 rev. *e page 12 of 13 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document are the tradema rks of their respective holders. package diagrams (continued) 28-lead thin small outline pack age type 1 (8 x 13.4 mm) z28 51-85071-*g 51-85074-*f 28-lead reverse type 1 thin small outline package (8x13.4 mm) zr28
cy62256 document #: 38-05248 rev. *e page 13 of 13 document history page document title: cy62256 256k (32k x 8) static ram document number: 38-05248 rev. ecn no. issue date orig. of change description of change ** 113454 03/06/02 mgn change from sp ec number: 38-00455 to 38-05248 remove obsolete parts from ordering info, standardize format *a 115227 05/23/02 gbi changed sn package diagram *b 116506 09/04/02 gbi a dded footnote 1. corrected package description in ordering information table *c 238448 see ecn aju added automotive product information *d 344595 see ecn syt added pb-free packages on page# 10 *e 395936 see ecn syt changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? added cy62256l?70snxi package in the ordering information on page # 10

▲Up To Search▲

Price & Availability of CY62256LL-70SNXCT

	To Download CY62256LL-70SNXCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .